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130
8018P–AVR–08/10
ATmega169P
Note:
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the
WGM12:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
15.11.2
TCCR1B – Timer/Counter1 Control Register B
Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
Table 15-4.
Waveform Generation Mode Bit Description(1)
Mode
WGM13
WGM12
(CTC1)
WGM11
(PWM11)
WGM10
(PWM10)
Timer/Counter Mode of
Operation
TOP
Update of
OCR1
x at
TOV1 Flag
Set on
0
Normal
0xFFFF
Immediate
MAX
1
0
1
PWM, Phase Correct, 8-bit
0x00FF
TOP
BOTTOM
2
0
1
0
PWM, Phase Correct, 9-bit
0x01FF
TOP
BOTTOM
3
0
1
PWM, Phase Correct, 10-bit
0x03FF
TOP
BOTTOM
4
0
1
0
CTC
OCR1A
Immediate
MAX
5
0
1
0
1
Fast PWM, 8-bit
0x00FF
BOTTOM
TOP
6
0
1
0
Fast PWM, 9-bit
0x01FF
BOTTOM
TOP
7
0
1
Fast PWM, 10-bit
0x03FF
BOTTOM
TOP
8
100
0
PWM, Phase and Frequency
Correct
ICR1
BOTTOM
9
100
1
PWM, Phase and Frequency
Correct
OCR1A
BOTTOM
10
1
0
1
0
PWM, Phase Correct
ICR1
TOP
BOTTOM
11
1
0
1
PWM, Phase Correct
OCR1A
TOP
BOTTOM
12
1
0
CTC
ICR1
Immediate
MAX
13
1
0
1
(Reserved)
–
14
1
0
Fast PWM
ICR1
BOTTOM
TOP
15
1
Fast PWM
OCR1A
BOTTOM
TOP
Bit
765
4
3
210
(0x81)
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
TCCR1B
Read/Write
R/W
R
R/W
Initial Value
0
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